Field
The disclosure relates generally to a voltage converter circuit and, more particularly, to a buck converter thereof.
Description of the Related Art
FIG. 1 is a circuit schematic of a buck converter and regulation loop. The buck converter comprises of an input voltage VIN 10, a ground VSS 20, an output voltage VOUT 30, an inductor L 40, a capacitor C 50, a high side switch SH 60, and a low side switch SL 70. The regulation loop comprises of a divider DIV 75, an operational amplifier OA1 80 with input VOUT/K and VREF signals, a current sensor RS 90, a sum function 92 with slope compensation, a comparator 95 with a positive input 94, and negative signal from OA1 80, an RS flip-flop 97 which provides an output signal 100 to the high side switch 60.
When operating at constant frequency, a clock ‘clk’ is periodically issued and set the magnetization ‘mag’ signal to ‘1’. The inductor current IL through inductor L 40 is sensed and converted to a voltage by a multiplication of Rs. Sometimes, a slope-compensation 92 is added, from those skilled in the art are aware of providing. So the comparator CP1 95 emits the signal ‘stop’ every-time the voltage (Rs.IL+Slope_Comp) 94 exceeds VEA. In other words VEA is the target for the maximum inductor current, also called the peak-current. VEA is regulated by the error amplifier (based on operational amplifier OA1 80 that also acts as the transconductance part of the loop filter) to adjust the required peak inductor current to regulate VOUT 30 to a value proportional to VREF.
As known of those skilled in the art, the ideal case would be to transfer all the input power to the output power. In practice, all the buck converters have losses and do not achieve 100% efficiency. Switching losses are made of the dynamic losses (ohmic losses in the power FETs during the transition in a few ns of the node LX) and of the gate-charge losses (the switch SH 60 is often a MOS transistor whose gate needs to be charged). As order of magnitude, during one period, a total charge of 5 nC to 10 nC is consumed for a 5V-input buck with a MOS that is 20 mΩ resistive. If the switching frequency is 2 MHz, this corresponds to a loss of 50 mW. Therefore, if VOUT is 1.0V and IOUT=50 mA, the output power is similar to the switching losses which makes the efficiency very poor. The standard technique is then to periodically skip the pulses (so to skip the activation of the switch SH) when the output load (so when the output power) is so low that the efficiency of the buck would be impacted by the switching losses. This leads to a disadvantage of a higher ripple on the output voltage node VOUT 30.
FIG. 2 is a timing diagram of pulse skip modulation. In the FIG. 2, a prior art method is illustrated for skipping the pulses. To understand the methodology, assume the output current load decreases. As shown in FIG. 1, the operational amplifier OA1 80 decreases VEA to decrease the peak (and thus average) inductor current IL, thus adapting the inductor current to the output load. The IL-curve (IL(CCM)) 230 of the FIG. 2 describes what would happen is high side switch SH and low side switch SL in the FIG. 1 are straight MOS switches: VEA decreases until IL(CCM) 230 average value is 0 A, corresponding to the OA output load. IL has its reverse current enabled in this case.
To decrease the switching losses, a Discontinuous Modulation (DCM) is illustrated (thick-line IL-curve 220) with two additions:
The first addition is a low-side switch SL is no longer a straight MOS but is implemented as an ideal diode: it has a low resistance when LX is lower than 0V (forward inductor current toward output) and it is OFF when LX is greater than 0V; this prohibits reverse current.
The second addition is the inductor current has a minimum peak value that supersedes the VEA-setting: so even if VEA requires a peak-current lower than the limit IPEAKMIN, the effective inductor peak-current is clamped down to this minimal value.
As a consequence, when the load current decreases and goes to 0 A (FIG. 2), the condition is as follows:                There is no reverse inductor current due to the ideal diode. So for the same peak-current setting by VEA, the average current in DCM is greater than in CCM. As a result, this leads to the delivery of more current to the output; this results in an increase in the output voltage VOUT and thus leads to the output amplifier OA1 to decrease further value of VEA.        This VEA decreases has no effect below the line in the figure; the inductor peak-current is maintained to the minimum value. As a result, the system delivers more current than needed to the output, and VOUT increases.        Based either on a voltage criterion (in the prior art) or on self-adjusting system (to be discussed), the DCM cycle is held (Pulse Skip Criterion of FIG. 2) until the output voltage VOUT decreases; this then proceeds to the condition, where pulses are restarted.        
To achieve the modulation as shown in FIG. 2, the prior art uses various methods, all having in common the use of the ideal diode for the low-side switch. These methods can be defined as two categories:                Parallel loop: In the Parallel Loop method, the inductor current is measured and if low enough, a pseudo-hysteretic method is used to achieve the modulation, as depicted in FIG. 2: it uses a (optional) high-level VOUT-threshold to start skipping the pulses and a low-level VOUT-threshold to re-start the pulses, as well as a dedicated peak-current comparator (to emulate the IPEAKMIN line constant peak current). This requires an extra comparator (voltage threshold) that also needs to be matched to OA1 in terms of accuracy, and also this creates a complicated swap between the hysteretic loop and the peak-current loop. However it has the advantage of deactivating the peak-current loop once the low-current is detected, thus saving consumption.        Main Loop: In the Main Loop methodology the peak-current control loop can be left operating, and another system is used as shown in FIG. 3. FIG. 3 is a prior art Pulse Skip Method. FIG. 3 comprises a first comparator CP1 310, a second comparator CP2 330, and a special latch 350 whose output is mag 370. Comparator CP1 310 has an input Rs.IL+slope compensation 315, and a second input VEA 320. Comparator CP2 330 has an input Rs.IL 335 and second input Rs (0.6 A). In addition to the comparator CP1 310, a second comparator CP2 330 compares the inductor current to a fixed value (e.g. 0.6 A) illustrated in the FIG. 2. A special latch waits until the two reset signals R1 325 and R2 345 go up. So if VEA 320 is very low and limits the peak inductor current to e.g. 0.3 A, the actual peak inductor current will still be 0.6 A, thus achieving the behavior as illustrated in FIG. 2. Yet, a voltage comparator is still needed to stop VOUT from increasing (as observed in FIG. 2), which requires the same matching as in the first method.        
Other methods associated with pulse frequency modulation, pulse-skipping modulation and additional methods have been described in the prior art.
U.S. Patent Application 2013/0294118 to So et al., an output estimation for a converter is described. An output current estimation for an isolated flyback converter with variable switching frequency control and duty cycle adjustment for both PWM and PFM modes is discussed. Fly-back converters that may operate over a wide range of power and would benefit from Pulse-Frequency-Modulation (PFM) and Pulse-Skipping-Modulation (PSM) that both vary the frequency while maintaining a relatively constant pulse width or duty cycle is discussed.
U.S. Pat. No. 7,898,235 to Seo, describes a method and apparatus for a voltage conversion, The voltage conversion for pulse width modulation (PWM) and pulse frequency modulation (PFM) is discussed.
U.S. Pat. No. 7,595,596 to Liu describes a power saving control circuit and method for OLED panels. The power stage is controlled by a control circuit. The power stage may be a buck converter, a boost converter, an inverter, or a fly-back voltage supplier. The control circuit may be, e.g., a pulse width modulation circuit, a pulse frequency modulation circuit, a pulse skipping modulation circuit, or a linear regulator.
U.S. Pat. No. 7,592,791 to Emira describes a DC-DC converter and method of improving the efficiency of a DC-DC converter at low load current levels using pulse skipping modulation (PSM) with controllable burst duration
U.S. Pat. No. 7,408,333 to Chen et al., describes voltage regulating modes a voltage converter. Three voltage-regulating modes, namely, the pulse-skipping mode, the pulse-width modulation mode and the pulse-frequency modulation mode are integrated, where the optimal conversion efficiency can be achieved in the whole load duration in any case.
In these prior art embodiments, the solution to establish an efficient buck converter utilized various alternative solutions.